The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure that includes an oxide resistive random access memory (ReRAM) co-integrated with a drain region of a field effect transistor (FET).
Many modern day electronic devices contain electronic memory. Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory retains its stored data in the absence of power, whereas volatile memory loses its stored data when power is lost. Resistive random access memory (ReRAM or RRAM) is one promising candidate for the next generation of non-volatile memory due to its simple structure and its compatibility with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes.
For oxide ReRAMs, electroforming of a current conducting filament is needed. This process relies on randomness and thus the position of the filament of the oxide ReRAM is not well controlled. This results in a higher forming voltage as the ReRAM cell is scaled and higher device variability. Also, oxide ReRAMs typically require a current control field effect transistor to form a 1T1R (e.g., one-transistor one-resistive element) structure. This makes the process integration complicated. Co-integration of a FET with an oxide ReRAM in tight spacing is thus needed.